In an implicit type, the clock generation is built in logic with latch. If the width of the triggered pulse is narrow then the latch acts like an edge triggered flip-flop, these are of two types: implicit type and explicit type. A PFF consists of a latch and pulse generator. This gives better powerĭepartment of Electronics and Communication Engineering TRP Engineering College (SRM GROUP), A PFF consists of single latch as compared with two latches in the conventional transmission gate (TG). Pulse triggered flip-flop (PT-FF) is considered as an alternative for the conventional transmission gate (TG) based or master-slave based edge triggered flip-flops. If the power consumed by the flip-flop is reduced then there will be reduction on total power consumption of the clock system. When a latch is enabled it becomes transparent, a flip-flop's output only changes on a single type (positive or negative going) of clock edge. The simple ones are commonly called latches using this terminology a latch is level- sensitive, whereas a flip-flop is edge-sensitive. Although the term flip-flop has historically referred generically to both simple and clocked circuits, in modern usage it is common to reserve the term flip- flop exclusively for discussing clocked circuits. Pulse triggered FF (P-FF) has been thought of a preferred various to the traditional master-slave based FF with in the applications of high speed operations -.įlip-flop can be simple (transparent or opaque) or clocked (synchronous or edge-triggered). It is also estimated that the power consumption of the clock system, which consists of clock distribution networks and storage elements, is as high as 20%- 45% of the total system power. In particular, digital styles today typically adopt intensive pipelining techniques and use several FF-rich modules. Keywords Flip-Flop, Pulse Triggered, Low Powerįlip-flops (FFS) are the fundamental storage parts used extensively altogether sorts of digital styles. Simulation is performed for various pulse triggered flip-flop to demonstrate the effectiveness of our proposed system using Micro wind 120-nm technology, analysis of power reduction is simulated by using micro wind tool. The transistor sizes of the delay inverter and pulse generation circuit are reduced for power saving. Pass-transistor logic based NAND gate is designed for pulse generation which reduces circuit complexity and enhances for faster discharge. The proposed method is pulse-triggered flip-flop (PT-FF) design based on a signal feed through scheme. TRP Engineering College (SRM GROUP), Tiruchirappalli – 621 105, IndiaĪbstract The flip-flop is the one of the major component in VLSI low power circuits. International Journal of Engineering Research & Technology (IJERT) Low Power Pulse Triggered Flip-Flop using Signal Feed- Through Scheme